This invention relates to a high-speed serial interface, especially in a programmable logic device (PLD), which may operate at different data rates.
It has become common for PLDs to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards—e.g., the XAUI (Extended Attachment Unit Interface) standard. In accordance with the XAUI standard, a high-speed serial interface includes transceiver groups known as “quads,” each of which includes four transceivers and some central logic.
In one implementation, each transceiver is divided into a physical medium attachment (PMA) portion or module which communicates with outside devices, and a physical coding sublayer (PCS) portion or module which performs serial processing of data, for transmission to, or that is received from, those outside devices. Currently available PMA modules and PCS modules overlap in terms of the data rates that each will support, but the maximum data rate of available PMA modules typically exceeds the maximum data rate of available PCS modules.
Commonly-assigned U.S. Pat. No. 6,888,376, hereby incorporated by reference herein in its entirety, discloses a serial interface in which, at higher data rates, two PCS modules are used with each PMA module. However, that solution leaves a PMA module corresponding to one of the two PCS modules unused, and reduces the number of channels in the interface by up to half, if all of the channels used in the device require higher data rates.
It would be desirable to be able to support currently available data rates in a programmable logic device serial interface without wasting up to half the capacity of the serial interface.